1. Field of the Invention
The present invention generally relates to integrated circuit chips and more particularly to electrostatic discharge protect devices for integrated circuit chips.
2. Background Description
As semiconductor device features are shrunk with each new technology generation, device insulating layers are thinned proportionately, i.e., "scaling". These thinner dielectric layers fail at lower voltages. Consequently, polysilicon gate structure scaling increases circuit sensitivity to voltage stress, electrical overstress (EOS) and electrostatic discharge (ESD) failures. These types of failures are a major concern in insulated gate field effect transistor (FET) technologies, typically referred to as MOSFET. This is especially true for MOSFET chips that interface to other chips or signals with voltages above that of the MOSFET chip itself.
FIGS. 1A-B, are cross-sectional views of a prior art protect device structures 100, 102. Each device includes a gate 104 insulated from a semiconductor body 106 by an insulator layer 08.
In FIG. 1A, the device 100 is a lightly doped drain (LDD) field effect transistor diode with a p-type diffusion 110 on one side of the gate 104 and an n-type diffusion 112 is on the opposite side. Nitride spacers 114 over lightly doped regions (not shown) on each side of the gate 104, insure that the edges of the gate 104 are spaced away from diffusions 110 and 112. Shallow trench isolation (STI) 116 is provided at each diffusion 110, 112 to isolate the device 100 from adjacent circuits.
In FIG. 1B a p-type diffusion 110 is on one side of and adjacent to the gate 104 and shallow trench isolation 118 separates the gate from n-type diffusion 112. In both of these prior art devices, the gate 104 is either n-type or p-type polysilicon.
Normally, integrated circuit (IC) chips include protect devices or diodes such as those in FIGS. 1A or 1B in interface circuits to provide the IC chip with added ESD protection. U.S. Pat. No. 5,629,544, entitled "Semiconductor Diode with Silicide Films and Trench Isolation" to Voldman et al. teaches using diode structures bound by polysilicon for bulk silicon and silicon on insulator (SOI) MOSFET applications. However, where MOSFET chips must interface with higher voltage signals or, chips operating at voltages above the MOSFET's native voltage, these polysilicon protect devices do not provide adequate protection. ESD type failures are the result of this inadequate protection.
Further, on some SOI chips ESD protection is provided by a lateral unidirectional bipolar type insulated gate transistor known as a Lubistor. Lubistors are also sensitive to the dielectric stress.
Thus, there is a need for thin oxide diodes that are less sensitive to dielectric failures from electric field stress.